1. Field of the Invention
The present invention generally relates to a cooperation circuit and, more particularly, to a cooperation circuit with a phase delay between the phase of the present-stage control signal and the phase of previous-stage control signal.
2. Description of the Prior Art
The cooperation circuit, currently used in large-current control, is generally controlled by internal switches with serial peripheral interface (SPI) bus, I2C bus, SM bus or PM bus, which results in drawbacks as follows:
1. External setting of addressing is required for I2C bus, SM bus or PM bus. The clock frequency is too low (less than 400 kHz) for high-frequency switching. For example, the clock frequency is required to be 60 MHz for 500-kHz pulse width modulation (PWM) with 7-bit resolution.
2. Even though the SPI bus is capable of using ring topology without external addressing, the aforementioned low clock frequency cannot match with the operation. Moreover, high clock frequency operation consumes much power and induces EMI and noise.
3. If the master needs to send the setting data such as duty, resolution, or phase shift . . . etc to the slave, the slaves should have internal osc/clock to count the duty, which adds the cost and power consumption. If external clock is used, it may result in high power consumption and EM interference. And even worse, if the clock frequency of each IC is different, the PWM frequency of each IC is different.
Therefore, there exists a need in providing a cooperation circuit without additional addressing that is capable of achieving low power consumption, low EMI and identical PWM frequency.